This course describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in static data flow graph implementation such as using streams, cascade stream, buffer location constraints, run-time parameterization and APIs to update and/read run-time parameters.
The emphasis of this course is on:
- Implementing a system-level design flow (PS + PL + AIE) and the supported simulation
- Using an interface for data movement between the PL and AI Engine
- Utilizing advanced MAC intrinsics to implement filters
- Utilizing the AI Engine library for faster development
- Applying advanced features for optimizing a system-level design
See also
- Xilinx training schedule and registration
- ACAP-AIE2 Designing with Versal AI Engine 2 course description.
