This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications to improve time to market.
The emphasis of this course is on:
- Describing the Xilinx PCI Express design methodology
- Enumerating various Xilinx PCI Express core products
- Selecting the PCI Express IP cores from the Vivado® Design Suite
- Generating PCI Express example designs and simple applications
- Identifying the advanced capabilities of the PCIe specification
This course also focuses on the AXI-Streaming interconnect.
What's New for 2021.1
- New labs: "Implementing the PCIe Block" and "Debugging the PCIe Block"
- All labs have been updated to the latest software versions
Please see full course description.
