Designing with the UltraScale and UltraScale+ Architectures

This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.

The emphasis is on:

• Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
• Describing improvements to the dedicated transceivers and Transceiver Wizard
• Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
• Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® Design Suite

What's New for 2022.1

• All labs have been updated to the latest software versions

See also:

• FPGA-US:  Designing with the UltraScale and UltraScale+ Architectures course description
• Xilinx training schedule and registration