Explore the IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IPI block designs using the Vivado® Design Suite.
This course focuses on:
- Creating an IPI block design using the Vivado Design Suite
- Creating your own custom IP via the IP packaging flow
- Using the IP integrator to add and configure the Versal® ACAP CIPS block and then to export the generated programmable device image (PDI)
- Configuring the AXI network on chip (NoC) to access DDR memory controllers in Versal ACAP devices
What's New for 2022.1
- Designing with the IP Integrator module: Added information on block design module referencing
- All labs have been updated to the latest software versions
See also:
- Full product description
- EMBD-88080: AMD / Xilinx Rapid Development Embedded Design
- EMBD-ZUPSA: Zynq UltraScale+ MPSoC for the System Architect
- FPGA-VDES1: Designing FPGAs Using the Vivado Design Suite 1
- FPGA-VDES2: Designing FPGAs Using the Vivado Design Suite 2
- FPGA-VDES3: Designing FPGAs Using the Vivado Design Suite 3
- FPGA-VDES4: Designing FPGAs Using the Vivado Design Suite 4
- Xilinx training schedule and registration
