C-based Design: High-Level Synthesis with the Vivado HLx Tool

This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool.

The focus of this course is on:

• Converting C/C++ designs into RTL implementations
• Learning the Vitis HLS tool flow
• Creating I/O interfaces for designs by using the Vitis HLS tool
• Applying different optimization techniques
• Improving throughput, area, latency, and logic by using different HLS pragmas/directives
• Exporting IP that can be used with the Vivado® IP catalog
• Downloading for in-circuit validation

What's New for 2022.1

• Optimizing for Throughput module: Added details on automatic array partitioning and using performance constraints to simplify loop-level pragma insertion
• All labs have been updated to the latest software versions

See also: 

• DSP-HLS:  C-based Design: High-Level Synthesis with the Vivado HLx Tool course description
• Xilinx training schedule and registration