Designing FPGAs Using the Vivado Design Suite 4

$1,600.00
SKU:
FPGA-VDES4
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Learn how to use the advanced aspects of the Vivado® Design Suite and AMD-Xilinx hardware.

The focus is on:

  • Applying timing constraints for source-synchronous and system-synchronous interfaces
  • Utilizing floorplanning techniques
  • Employing advanced implementation options
  • Utilizing AMD-Xilinx security features
  • Identifying advanced FPGA configurations
  • Debugging a design at the device startup phase
  • Using Tcl scripting in non-project batch flows

This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

What's New for 2022.1

  • Added content on timing closure techniques to reduce logic delay and net delay, improve clock skew, and improve clock uncertainty
  • Added content on Abstract Shell for DFX
  • All labs have been updated to the latest software versions

 See also: