This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.
The course provides experience with:
- Creating a Vivado Design Suite project with source files
- Simulating a design
- Performing pin assignments
- Applying basic timing constraints
- Synthesizing and implementing
- Debugging a design
- Generating and downloading a bitstream onto a demo board
What's New for 2020.1
- HDL Coding Techniques: Example code for register initialization
- Vivado IP Flow: Reorganization of module and update of synthesis flow
- Introduction to Clock Constraints: More details on clock latency
See also: