Designing FPGAs Using the Vivado Design Suite 1

This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with:

• Creating a Vivado Design Suite project with source files
• Simulating a design
• Performing pin assignments
• Applying basic timing constraints
• Synthesizing and implementing
• Debugging a design
• Generating and downloading a bitstream onto a demo board

What's New for 2022.1

• Added new modules:
• Introduction to Clocking and Static Timing Analysis (STA)
• Setup and Hold Violation Analysis

• All labs have been updated to the latest software versions

See also: 

• FPGA-VDES1:  Designing FPGAs Using the Vivado Design Suite 1 course description
• Xilinx training schedule and registration