Designing FPGAs Using the Vivado Design Suite 2

Learn how to build a more effective FPGA design:

The focus is on:

• Using synchronous design techniques
• Utilizing the Vivado® IP integrator to create a sub-system
• Employing proper HDL coding techniques to improve design performance
• Debugging a design with multiple clock domains

This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

What's New for 2022.1

• Added information on block design referencing
• Added new modules:
• Block Design Containers in the Vivado IP Integrator
• Versal ACAP: Hardware Platform Development Using the Vivado IP Integrator

• Added content on power awareness
• All labs have been updated to the latest software versions

See also: 

• FPGA-VDES2:  Designing FPGAs Using the Vivado Design Suite 2 course description
• Xilinx training schedule and registration

See also: 

• FPGA-VDES2:  Designing FPGAs Using the Vivado Design Suite 2 course description
• Xilinx training schedule and registration