Designing FPGAs Using the Vivado Design Suite 3

Learn how to effectively employ timing closure techniques.

This course includes:

• Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
• Showing optimum HDL coding techniques that help with design timing closure
• Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design

This course builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.

What's New for 2022.1

• Added information on clock domain crossing (CDC)
• Added lab and module: Intelligent Design Runs (IDR)
• Added lab: Increasing Design Performance Using Report QoR
• All labs have been updated to the latest software versions

See also:  

• FPGA-VDES3:  Designing FPGAs Using the Vivado Design Suite 3 course description
• Xilinx training schedule and registration